(China (Mainland))
Product Summary
The Spartan-II Field-Programmable Gate Array XC2S50-5TQG144C gives users high performance, abundant logic resource, and a rich feature set, all at an exceptionally low price. The XC2S50-5TQG144C offers densitie ranging from 15,000 to 200,000 system gates, as shown in Table 1. System performance is supported up to 200 MHz. Features of the XC2S50-5TQG144C include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The XC2S50-5TQG144C is a superior alternative to mask-programmed ASICs. It avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).
Parametrics
XC2S50-5TQG144C absolute maximum ratings: (1)VCCINT Supply voltage relative to GND(2) -0.5~3.0 V; (2)VCCO Supply voltage relative to GND(2) –0.5 4.0 V; (3)VREF Input reference voltage –0.5 3.6 V; (4)VIN Input voltage relative to GND(3) 5V tolerant I/O(4) –0.5~5.5 V; (5)TSTG Storage temperature (ambient) –65 +150 ℃; (6)TJ Junction temperature - +125 ℃.
Features
XC2S50-5TQG144C features: (1)Pin-to-Pin Parameters; (2)IOB Switching Characteristics; (3)Clock Distribution Characteristics; (4)DLL Timing Parameters; (5)CLB Switching Characteristics; (6)Block RAM Switching Characteristics; (7)TBUF Switching Characteristics; (8)JTAG Switching Characteristics.
Diagrams
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 XC2S50-5TQG144C |
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IC SPARTAN-II FPGA 50K 144-TQFP |
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XC2S100 |
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XC2S100-5FGG256C |
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IC SPARTAN-II FPGA 100K 256-FBGA |
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